LVDS SERDES reference clock enforcement change in 18.1

Hi Richard ,

What being communicated by Anand on October 10, 2018 is correct. We've been discussed internally back and forth regarding this inquiry. At design perspective, we do not encourage to use TX ref clk for LVDS SERDES. Quartus II Tools should have and had to blocked this setting even in earlier version released.

So, what being captured in Table 9 in LVDS SERDES Guide is determined on how this operational setting going to works. Any standalone interfaces less than 23 channels required a refclk pin in within the same IO Bank whereby for those interfaces that consist of more than 23 channels, we would recommend to use channels 23-71 for refclk input sharing.

On the other hand, we are working on a fix on future release (Tentative) to have more error checking. This will make sure users isn't using the clock from another IOPLL or some other sources from IO Bank.

For your PCB design, we would recommend to used Quartus V18 if this suite yours product or change your design based on later Quartus LVDS SERDES characterizations. Otherwise, this options will not be allowed from Quartus V18.1 and onward.

I hope this addressed yours doubt and thanks for using this forum to get support.

Thanks,

Joseph

Intel Customer Support