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Altera_Forum
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17 years ago

LVDS Assignment in Quartus

Hi, I am using Quartus II 7.2 for programming a Stratix III device. I have an 8 channel (12 bit) LVDS input that I wish to deserialize and 2 LVDS clocks. I believe the megafunction for deserializa...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Hi,

I decided to go with LVDS DESER megafunction to deserialize into 2x6 bitstream and them multiplex it into 12 parallel signals (i have yet to figure that out though). The problem with alt_lvds is that it is not aligning the data properly. I want the first bit to be registered at the positive edge of the clock. Whereas the megafunction registers the input at positive edge to be the third bit. I tried giving phase difference in the options available in the megafunction window. Tried all the phase differences 45,90,180,270....but the output still remains the same.. Am I missing something here. Attached is a pic of the output.

Jatin