Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

lpm_latch makes quartus_map run much longer

I am integrating a netlist design which has about 40K latches with async clear or set.

If I use LPM_LATCH for these latches then quartus takes very long to map.

If I use simple LATCH but pull the async ctrls to the D and ENA pins then

it finishes much faster. Obviously i would like to use the lpm_latch but I don;t

know how to make the tool run fast. Please give some pointers..

I am using stratix iv and quartus 11.

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    With recent FPGA families(e.g. Stratix IV), latches can be only implemented as logic loops, because asynchronous functions except for clear have been removed from register capabilities. I don't however understand the difference between the LPM_LATCH and "simple LATCH" implementation.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Hello Sir,

    Many thanks for a reply.

    Simple latch is just LATCH (.q , .ena, .d0

    lpm_latch has this with aclr and aset.

    I need aclr and aset to port my design.

    How do i instantiate a latch with clear (without using a combinational loop)

    --- Quote Start ---

    With recent FPGA families(e.g. Stratix IV), latches can be only implemented as logic loops, because asynchronous functions except for clear have been removed from register capabilities. I don't however understand the difference between the LPM_LATCH and "simple LATCH" implementation.

    --- Quote End ---

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    I have to say - filling a Stratix IV with latches seems like a massive waste of money. Why are you using latches, and not registers?