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Altera_Forum's avatar
Altera_Forum
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14 years ago

lpm_latch makes quartus_map run much longer

I am integrating a netlist design which has about 40K latches with async clear or set. If I use LPM_LATCH for these latches then quartus takes very long to map. If I use simple LATCH but pull th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Hello Sir,

Many thanks for a reply.

Simple latch is just LATCH (.q , .ena, .d0

lpm_latch has this with aclr and aset.

I need aclr and aset to port my design.

How do i instantiate a latch with clear (without using a combinational loop)

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With recent FPGA families(e.g. Stratix IV), latches can be only implemented as logic loops, because asynchronous functions except for clear have been removed from register capabilities. I don't however understand the difference between the LPM_LATCH and "simple LATCH" implementation.

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