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Altera_Forum
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14 years ago

lpm_constant and synchronous between jtag clock and systemglock

Hi, I have used for a long time those lpm_constant in Quartus (9.1 SP1 in my case). Boards seems to work correctly but I see the following in Quartus, with Design Assistant :

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Critical Warning: (High) rule d101: data bits are not synchronized when transferred between asynchronous clock domains. (Value defined:2). Found 138 asynchronous clock domain interface structure(s) related to this rule.

Critical Warning: Node "const_parm:\parm_block:param_from_ismce|lpm_constant:lpm_constant_component|lpm_constant_7i8:ag|sld_mod_ram_rom:mgl_prim1|constant_update_reg[1]"

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Should I add registers for synchronous?

OR could I safely ignore those warnings which only concern lpm_constant ?

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    By Altera Service Request, the solution is here : http://quartushelp.altera.com/11.1/master.htm#mergedprojects/verify/da/comp_file_rules_synch_no.htm

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    If the data bits belong to single-bit data, the following guidelines can prevent metastability problems during synchronization of the data bits:

    Synchronize each data bit with the appropriate number of cascading registers in the receiving asynchronous clock domain.

    Trigger cascading registers on the same clock edge.

    Altera recommends against using logic between the output of the transmitting clock domain and the cascaded registers in the receiving asynchronous clock domain.

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