lpm_constant and synchronous between jtag clock and systemglock

By Altera Service Request, the solution is here : http://quartushelp.altera.com/11.1/master.htm#mergedprojects/verify/da/comp_file_rules_synch_no.htm

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If the data bits belong to single-bit data, the following guidelines can prevent metastability problems during synchronization of the data bits:

Synchronize each data bit with the appropriate number of cascading registers in the receiving asynchronous clock domain.

Trigger cascading registers on the same clock edge.

Altera recommends against using logic between the output of the transmitting clock domain and the cascaded registers in the receiving asynchronous clock domain.

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