Looping problem faced since loops are not synthesizable. Any other way?

So echo is coming in from the outside world. When the signal arrives on the FPGA pin, it will probably not be lined up with the FPGA clock's edge. Therefore you may miss some data because it arrives too early or too late. Because of this your capture register may have an undetermined value (not 0 or 1) when the clock edge triggers in the always block. This is called metastability: https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/wp/wp-01082-quartus-ii-metastability.pdf

To solve the asynchronous problem you can write code that will implement a synchronizer chain. Here is a great example of the implementation with the code: https://daffy1108.wordpress.com/2014/06/08/synchronizers-for-asynchronous-signals/ . As you can see you just need to include 1 more always block.

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assign distance_o = (dist_counter * 340) << 1 you are bitshifting in the wrong direction..... if you want to divide by 2, it would be a bitshift to the right >>

why not multiply by 170...... instead of 340/2