Looping problem faced since loops are not synthesizable. Any other way?

Your code is complete. Always blocks will run continuously, so once you reset counter, it will just continue incrementing in the 'counter <= counter + 1' statement.

Your if statements make no sense, however. The symbol '<=' is a non blocking assignment, but in logic (if statement) it means less than or equal to. Your if statements should be changed to == or >= otherwise they will all trigger at once... Please review your code.

You also want to put 'or posedge reset' in the sensitivity list. Next, since 'echo' is an asynchronous input, you should probably have some synchronizer chains to bring in the data into the FPGA's clock domain, or at least put some debounce logic.... not sure how clean your 'echo' signal's edge will be when it pops high.