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It sounds like you're going about HDL coding completly wrong. It is not like software, it is hardware. When you synthesise, loops are unrolled so that the worst case can be generated, hence the loop iteration limit. I dont know what your loop is doing, but it sounds like it's generating a long logic chain, which is not going to be very useful for you.
Did you draw out a sketch of the expected hardware before you wrote any code? HDL stands for Hardware description language, so if you dont know what you're describing, how do you expect to write the code?
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Thank you, Tricky, for your response. You are correct, of course, as I am trying to use my DE2-70 board as a microcontroller without setting one up using Qsys. In a nutshell, I am just playing with the board and was trying to write a Sudoku solver. I am doing a brute force attempt at trying numbers in each blank square using a FSM to control the placement of new numbers and the checking for duplicates. Everything works well except for the function that checks a quadrant for duplicates. That is where I get the error. What is puzzling to me is why changing the range in the 2nd "for loop" can suddenly cause the error to disappear. That makes no sense to me at all.
As far as hardware goes, I am not a designer of hardware, I am a retired businessman who loves to play with microcontrollers and have found the FPGA world has some neat possibilities. So I was letting Quartus and Verilog do all of the dirty work so that I could watch everything progress (showing progress on the HEX display and the LCD).
I have attached the function code in question if that is helpful. Again thank you for taking the time to respond and I would appreciate any further comments that anyone may have.
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