Forum Discussion
Altera_Forum
Honored Contributor
11 years agoIt sounds like you're going about HDL coding completly wrong. It is not like software, it is hardware. When you synthesise, loops are unrolled so that the worst case can be generated, hence the loop iteration limit. I dont know what your loop is doing, but it sounds like it's generating a long logic chain, which is not going to be very useful for you.
Did you draw out a sketch of the expected hardware before you wrote any code? HDL stands for Hardware description language, so if you dont know what you're describing, how do you expect to write the code?