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Altera_Forum
Honored Contributor
18 years agoTo improve routability, see the Quartus handbook, Volume 2, Section III, Chapter 8. There is a "Routing" section under "Resource Utilization Optimization Techniques (LUT-Based Devices). There is a "Reduce Routing Time" section under "Compilation-Time Optimization Techniques".
A couple of ways in addition to the interconnect usage messages to tell whether you have a routing problem: The Fitter messages might have more than one placement and routing attempt with this message after each aborted attempt: --- Quote Start --- Info: Can't fit design in device - retrying with increased optimization, which may result in a longer processing time --- Quote End --- The routing time might be longer than normal compared to the placement time. It is normal for routing time to be a third to half the placement time.