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Altera_Forum's avatar
Altera_Forum
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18 years ago

Long runtimes for Quartus II

Hi, I'm trying to run the following flow with Quartus: analysis and synthesis -> fitting -> assembler. I used the following two approaches: A. Give Quartus my RTL source files for analysis and...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

The main three stages of fit time, placement, routing and physical synthesis(if on), all give messages in the .fit.rpt for how long they took, so these are worth comparing. Also compare the device resources being used. Note that Design Compiler is an ASIC tool. I believe they have a companion tool called FPGA Compiler, but I'm not sure if that's still available.