Long place and route after adding logic lock regions

the large combinational loop is tristate communication logic implemented with multiplexers, i've checked by adding registers to the outputs of the logic feeding the communication structure and compile time goes from 1 hour to 2 minutes, somewhere in the handbook is a warning about combitational loops causing the design tools to go into large computational loops, i don't know if this may be the cause of my problem. The current solution that i am exploring is to partition the design leaving the interconection logic out of it and then adding it, but i am kinda new with altera tools so any suggestions will be appreciated.