--- Quote Start ---
In the past, when quartus could not fit designs, it usually bailed on me after about 8 hours of place and route.
I added logic lock regions so I could isolate partitions for timing and close timing on each individually. However, after adding them, p&r has been running for 44 hours.
Has anyone run p&r for this long and had a successful result? The logic utilization is about 55%. My main problem is interconnects for the timing.The logic lock regions were set to auto size/location (this is my first iteration).
Also, if anyone knows of a nice guide on timing closure with quartus, it would be awesome :D. I've only become frustrated with TimeQuest and chip planner and the altera docs. It's for a Stratix II GX chip.
--- Quote End ---
I assume that your first ( 8hours) was without any partition or logiclock setting. The long P&R run with a utilization of 55% indicates, in my point of view, that you have a routing problem in your design. Do you have large multiplexer or special requirements for memory ( bit enable) in your design ?
What do mean with "My main problem is interconnects for the timing" ?
Honored Contributor
