Lite: 17.1 upgrade to 20.1, now ramstyle not working, getting logic, not M9K blocks, won't fit

You described a set of registers in a Verilog Design File (.v) or VHDL Design File (.vhd) that behave as RAM. Analysis & Synthesis then replaces the registers with a RAM node that will later infer an instance of the altsyncram megafunction to implement the functionality of the registers using the memory blocks in the target device.

For further information related to this error, you can refer to this link:
https://www.intel.com/content/www/us/en/programmable/quartushelp/current/index.htm#msgs/msgs/winfer_ram_pass_through_logic_inserted_altsyncram.htm