Linux Qsys Now "platform designer", ALT_PLL Altera FPGA IP doesn't save, crash.

Hi Rsee, I loaded the file you sent back, I argue is just same I sent you.

Please OPEN QSYS (Platform Designer) LINUX version and try modify PLL settings:

Input clock 50MHz not 100

C1 Clock need a multiplier 2

C2 clock need a divider 5 to output 10Mhz clock

C3 ex set to 200MHz require a multiplier 4.

DSave and reopen, check change are on file.

If you can setup on Linux, and send back, then and only then you tested issue.

Quartus installed on Ubuntu 18.02_4 doesn't work so I cannot test till now.... I open another issue soon.

regards