Forum Discussion

RRomano001's avatar
RRomano001
Icon for Contributor rankContributor
6 years ago

Linux Qsys Now "platform designer", ALT_PLL Altera FPGA IP doesn't save, crash.

Linux Qsys Now "platform designer", from old time still has trouble never addressed. ALT_PLL Altera FPGA IP open in a small window with scroll bar, if something is touched in this state after long ...
Rahul_S_Intel1's avatar
Rahul_S_Intel1
Icon for Frequent Contributor rankFrequent Contributor
6 years ago
Hi , I have tried to test on the Quartus 18.1 standard ( Os Linux) and can able to successfully compile the design. And for me there is difficulty in testing the Quartus lite in linux environment, so could not able to do on that apology from myside