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RRomano001's avatar
RRomano001
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7 years ago

Linux Qsys Now "platform designer", ALT_PLL Altera FPGA IP doesn't save, crash.

Linux Qsys Now "platform designer", from old time still has trouble never addressed. ALT_PLL Altera FPGA IP open in a small window with scroll bar, if something is touched in this state after long ...
Rahul_S_Intel1's avatar
Rahul_S_Intel1
Icon for Frequent Contributor rankFrequent Contributor
7 years ago
The design file is wrong, I could not able to detach the content, I have tried to create a simple PLL and it is working
  • RRomano001's avatar
    RRomano001
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    7 years ago

    Hi RSree, test on Linux? I am not interested about Win, too slow and unreliable.

    Again a base project, generate PLL saving as is no edit allowed after create.

    It is not working and I see this problem also on other distribution.