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RRomano001's avatar
RRomano001
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6 years ago

Linux Qsys Now "platform designer", ALT_PLL Altera FPGA IP doesn't save, crash.

Linux Qsys Now "platform designer", from old time still has trouble never addressed. ALT_PLL Altera FPGA IP open in a small window with scroll bar, if something is touched in this state after long ...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
6 years ago

I'm not sure why the old Megawizard is showing up in a new version of Quartus. I'd recommend simply deleting the PLL component from your system design and re-adding it.

#iwork4intel

  • RRomano001's avatar
    RRomano001
    Icon for Contributor rankContributor
    6 years ago

    Hi Sstrell, this issue as I wrote is still present from revision 15.0 When I learned how to write My Ip core modules.

    Also in a new design if I add ALT_PLL has same behavior. See this

    Enlarge, edit parameter then finish

    Finish result in not saved PLL

    Step 3 add ALT_PLL, enlarge then two times finish button.

    step 4, edit Alt_PLL, just configure clock input 50MHz, C0 to 100MHz, c1 10MHz as from step 2, finish finish and IP remain as is from step 3.

    Delete add again same deterministic sequence. Alt_PLL_Reconfigure has same issue, other IP work like a charm.

    This as I stated never changed from at almost revision 15.0, I had no previous revision installed,

    Regards

    Roberto