Forum Discussion
RRomano001
Contributor
ContributorLinux Qsys Now "platform designer", ALT_PLL Altera FPGA IP doesn't save, crash.
Linux Qsys Now "platform designer", from old time still has trouble never addressed. ALT_PLL Altera FPGA IP open in a small window with scroll bar, if something is touched in this state after long ...
RRomano001Contributor
ContributorWhen enlarged as shown just save if one clock output is selected (sometimes) again editing never succed and next open show new parameter not held.
After succesful add I try'd two times add 3 more clock for 200, 250 and 10MHz, changes never appear on .qsys file.
Project is shareable just removing two IP core.
