License: Compilation Error

--- Quote Start ---

Hello Together!

When I compile my project I get following error message: Current license file does not support incremental compilation (and I will not use it :-)).

That happens since I'm clicked "Add Node to SignalTap II Logic Analyzer". My next compilation shows mentioned message. Removing generated files from project didn't solve the problem. I also checked .qsf-file for entry INCREMENTAL_COMPILATION FULL_INCREMENTAL_COMPILATION as mentioned in Quartus II Help document but there is no word INCREMENTAL at all. In window "Settings" "Incremental Compilation" I couldn't select anything.

Used Version:

Quartus II 9.0 Buid 235 Web Edition

Service Pack Installed: 2

Help Version: Quartus II Help Version 9.0

Thanks for your support!

Best regards

R. Schrauth

--- Quote End ---

Hi,

are you using Signaltap ?

Kind regards

GPK

Hi GPK,

I don't use Signal Tap II Analyser ("Settings", "SignalTap II Logic Analyser", "Enable Signal Tap Logic Analyser" is OFF). To give a complete overview I add all error messages which occure:

Error: Current license file does not support incremental compilation

Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings

*Error: Peak virtual memory: 190 megabytes

*Error: Processing ended: Thu May 20 09:45:25 2010

*Error: Elapsed time: 00:00:07

*Error: Total CPU time (on all processors): 00:00:04

Error: Quartus II Full Compilation was unsuccessful. 3 errors, 0 warnings

I'm not familiar with HDL-programming language and use only schematics. Are there any entries in files which force to use incremental compilation?

Kind regard

R. Schrauth

--- Quote Start ---

Hi GPK,

I don't use Signal Tap II Analyser ("Settings", "SignalTap II Logic Analyser", "Enable Signal Tap Logic Analyser" is OFF). To give a complete overview I add all error messages which occure:

Error: Current license file does not support incremental compilation

Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings

*Error: Peak virtual memory: 190 megabytes

*Error: Processing ended: Thu May 20 09:45:25 2010

*Error: Elapsed time: 00:00:07

*Error: Total CPU time (on all processors): 00:00:04

Error: Quartus II Full Compilation was unsuccessful. 3 errors, 0 warnings

I'm not familiar with HDL-programming language and use only schematics. Are there any entries in files which force to use incremental compilation?

Kind regard

R. Schrauth

--- Quote End ---

Hi,

maybe I found your problem. I assume you tried to use signaltap, right ?

Look into your <>.qsf . Do you find a line like this :

set_global_assignment -name PARTITION_NETLIST_TYPE POST_FIT -section_id Top

If yes, remove this line and all should work.

When you try to use signaltap and your node selection is set to "Signaltap post-fitting"

you will be ask to set the Top partition to "Post-fit". Unfortunately this means incremental

compilation, which is not supported by the Web Edition. I would say that is a bug or at least a weakness of this Quartus Version.

Kind regards

GPK

Hi GPK,

sorry, but entry you mentioned isn't there. I only found this: "set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top". I attached my .qsf file as pdf. Perhaps you could find the wrong entry easily.

Kind regards

R. Schrauth

--- Quote Start ---

Hi GPK,

sorry, but entry you mentioned isn't there. I only found this: "set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top". I attached my .qsf file as pdf. Perhaps you could find the wrong entry easily.

Kind regards

R. Schrauth

--- Quote End ---

Hi,

now I can only guess. Add following line in the qsf :

set_global_assignment -name INCREMENTAL_COMPILATION OFF

Kind regards

GPK

Hello,

thanks for your support but I couldn't solve the problem. Finally I designed a new project and entered the whole stuff again. It took few hours but now compilation works :-).

Kind regards

R. Schrauth