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Hi GPK,
I don't use Signal Tap II Analyser ("Settings", "SignalTap II Logic Analyser", "Enable Signal Tap Logic Analyser" is OFF). To give a complete overview I add all error messages which occure:
Error: Current license file does not support incremental compilation
Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings
*Error: Peak virtual memory: 190 megabytes
*Error: Processing ended: Thu May 20 09:45:25 2010
*Error: Elapsed time: 00:00:07
*Error: Total CPU time (on all processors): 00:00:04
Error: Quartus II Full Compilation was unsuccessful. 3 errors, 0 warnings
I'm not familiar with HDL-programming language and use only schematics. Are there any entries in files which force to use incremental compilation?
Kind regard
R. Schrauth
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Hi,
maybe I found your problem. I assume you tried to use signaltap, right ?
Look into your <>.qsf . Do you find a line like this :
set_global_assignment -name PARTITION_NETLIST_TYPE POST_FIT -section_id Top
If yes, remove this line and all should work.
When you try to use signaltap and your node selection is set to "Signaltap post-fitting"
you will be ask to set the Top partition to "Post-fit". Unfortunately this means incremental
compilation, which is not supported by the Web Edition. I would say that is a bug or at least a weakness of this Quartus Version.
Kind regards
GPK
Honored Contributor
