Library Mapping File Help

Can you elaborate? You can write structural code if you want, but there's no such thing as an AND, OR or MUX in the FPGA. It's all LUTs(and supporting logic like carry-chains), so unless you write LUTs, which I recommend against, then synthesis has to map to what's physically in the part. What might help is explaining why you want it to do this. My experience is writing low-level code is painful, slow, and provides very little benefit. I would only do it as a point solution.