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Altera_Forum
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8 years ago

LFSR doesn't generate random values during simulation Ask

I am new to VHDL. I made this LFSR but don't know why it is stuck between the initial seed value and the other XOR value. I am working with Altera Quartus 16 Lite and ISim. Here is the link https:...
Altera_Forum's avatar
Altera_Forum
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8 years ago

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Yes you are right, its ModelSim

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My example is Fibanocci for your case of 16 bits

shiftreg(1) <= shiftreg(16) xor shiftreg(15) xor shiftreg(13) xor shiftreg(4); --feeback taps

shiftreg(16 downto 2) <= shiftreg(15 downto 1); -- shift