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Altera_Forum
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8 years ago

LFSR doesn't generate random values during simulation Ask

I am new to VHDL. I made this LFSR but don't know why it is stuck between the initial seed value and the other XOR value. I am working with Altera Quartus 16 Lite and ISim. Here is the link https:...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

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I am new to VHDL. I made this LFSR but don't know why it is stuck between the initial seed value and the other XOR value. I am working with Altera Quartus 16 Lite and ISim.

Here is the link https://stackoverflow.com/questions/45486770/lfsr-doesnt-generate-random-values-during-simulation?noredirect=1#comment77935100_45486770 to the original question as I cannot post the code and problem in here as it exceeds the allowed character length.

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Here is example of 20 bit LFSR(20 downto1):

--clocked process and iitial seed of nonzero

shiftreg(1) <= shiftreg(17) xor shiftreg(20);

shiftreg(20 downto 2) <= shiftreg(19 downto 1);