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Altera_Forum's avatar
Altera_Forum
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8 years ago

LFSR doesn't generate random values during simulation Ask

I am new to VHDL. I made this LFSR but don't know why it is stuck between the initial seed value and the other XOR value. I am working with Altera Quartus 16 Lite and ISim. Here is the link https:...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

For a start, most of the bus is just assigned to itself, hence the no changing:

Each set of bits:

[15:11] : assigned to itself

[10] toggles, as you just xor it with the LSB

[9:5] assigned to itself

[4] toggles, as just xored with LSB

[3:0] assigned to itself.

So this will explain what you are seeing.

& is the concatenate operator in VHDL, not and.