less pre calculating possible ?

Hi,

First cyclone is not (poor), don't let Altera people here that...

It has plenty of resource to get you busy for a year.

If you mean that things were reduced and optimised away then it is because you asked the compiler to do that and possibly you ended up with few wires if at all. There is no such option as precalculate on/off. Your design entry determines any precalculations and any left as hardware. Your request is paradoxical: do you want to precalculate or do want more resource to calculate??

well, let me try to explain an example.

i tried to use the sieve of erastosthenes (http://en.wikipedia.org/wiki/sieve_of_eratosthenes) (http://en.wikipedia.org/wiki/sieve_of_eratosthenes)

So i wrote this in verilog together with a counter.

each second :

- calculate next prime number

- show number on 7-segment

and it works fine, but the problem is that it does not scale.

If i set the numbers to work on to be <15 i already need 18.000 logic elements but it works as it should.

if i set it higher i need even much more elements....

But what i want : no matter how huge the numbers get, it should still work.

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i finally realised that quartus is precalculating nearly everything

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Looks like a basic misunderstanding of how such operations can be implemented effectively in hardware logic respectively a hardware description language. It's very different from ususal sequential programming.

yes, as i said i'm all new to this :o

so, there is NO possibility to calculate this kind of functions in hardware ?

i don't care if it's slow.

Hi,

There is a gray line between applications that should be done in software and those done in firmware(e.g.HDL).

FPGAs can implement both; firmware for direct hardwiring of functionality giving maximum speed and software(nios) for slower work that depends on fetch-execute cycles.

Generally, complex slow algorithms are done in software and fast intensive data processing in firmware. So I don't see any reason not to use software to search for the largest prime number so far. In fact all keyboard/display issues that interface with human beings and other creatures can be done in software without speed problems.

In all cases there will be a limit of the finite representation, you can't go towards that infinity of mathematicians.

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so, there is NO possibility to calculate this kind of functions in hardware ?

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Of course it's possible. But you have to serialize the operation in a suitable way. An iteration over the intended number interval can e.g. process one value per clock cycle. But this has to be defined explicitely, not by a HDL for construct, that has the purpose of specifying parallel processing.

Thanks for explaining :)

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Of course it's possible. But you have to serialize the operation in a suitable way

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Do you maybe know an example on how to do this ?

Any website or tutorial for ?

i only worked with verilog till now, because i thought i can do everything with that :o