Honored Contributor
Honored ContributorHi mushussain ,
You can use PLL and Counter IP from QSYS. or find the code below and modify as per your requirement. Check the attached image. https://alteraforum.com/forum/attachment.php?attachmentid=14324&stc=1
Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity comparator is
port( Clk:in std_logic;
led_1: out std_logic;
led_2: out std_logic
);
end comparator;
architecture body3 of comparator is
signal cnt:std_logic_vector(2 downto 0):=(others=>'0');
begin
process (clk)
begin
if rising_edge(clk) then
cnt<=cnt+'1';
if(cnt="111")then
cnt<=(others=>'0');
end if;
end if;
end process;
process (clk,cnt)
begin
if (cnt<="011")then
led_1<='0';
led_2<='1';
else
led_1<='1';
led_2<='0';
end if;
end process;
end body3;
