Latency and delays

The word (Latency) is context dependant.

every (data path based) digital system outputs data after a number of clock periods. The worst case is a deep interleaver for example.

If you convert the clock periods to absolute time then an increase of clock speed means less latency in absolute time for same number of clocks.

i believe Tricky mentioned this in one of your other threads.

you can pipeline a design by registering signals between combinational logic. as you add more registers in a given logic path, the amount of combinational logic between registers decreases. less combinational logic means less propagation delay, which means you can clock the registers faster, and hit a higher fmax.

this is highly design dependent. stacking input registers, for example, will not break the combinational logic into smaller pieces and increase fmax. the logic itself has to be segmented and registered in between.

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more pipelining/registering means more latency (number of clocks between input and output).

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Thanks for your replies, pancake and kaz.

Forgive my lack of understanding but I still find the following part a bit confusing.

The increase of fmax = more calculations per sec, but also = longer for output to be calculated?

Doesn't the "longer for output to be calculated" part mean that the calculation is slower?

Hope this makes sense.

Best regards,

Chris

say you have a design with a pipeline depth of 10. it runs at 100 MHz. you put your data in at time=0, and at time = 10*(1/100,000,000) seconds, you receive your output result. in this case, a new result will be calculated every 1/100,000,000 seconds.

in another version of the design, you only have a pipeline depth of 1. it only runs at 10 MHz. you put your data in at time=0, and at time = 1*(1/10,000,000) seconds, you receive your result. in this case a new result will be calculated every 1/10,000,000 seconds.

the 100 MHz design has much better throughput and the same "real-world" time latency (but 10 actual clock cycles) as the 10 MHz design at the expense of 10x the register usage.

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The increase of fmax = more calculations per sec, but also = longer for output to be calculated?

Doesn't the "longer for output to be calculated" part mean that the calculation is slower?

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Chris, please google "latency vs. throughput".

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say you have a design with a pipeline depth of 10. it runs at 100 MHz. you put your data in at time=0, and at time = 10*(1/100,000,000) seconds, you receive your output result. in this case, a new result will be calculated every 1/100,000,000 seconds.

in another version of the design, you only have a pipeline depth of 1. it only runs at 10 MHz. you put your data in at time=0, and at time = 1*(1/10,000,000) seconds, you receive your result. in this case a new result will be calculated every 1/10,000,000 seconds.

the 100 MHz design has much better throughput and the same "real-world" time latency (but 10 actual clock cycles) as the 10 MHz design at the expense of 10x the register usage.

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Thanks for explaining in great detail. I think I finally got it!

So in the 100MHz design, I would get 10 results at once, instead of only one result in the 10 MHz case?

Thanks to vjalter as well, that really helped as well, guess i was searching the wrong terms, I kept googling "output latency vs clock frequency" and kept getting random stuff.

Thanks everyone. Makes much more sense now.

Best regards,

Chris

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no, the results still come serially (1 at a time, not 10), but you could run 10x the data through the system during the same period of time.

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Ok ok then does that mean that the circuit with a pipeline depth of 1 stays idle until its result comes out?

But are there conditions where increasing the pipeline depth doesn't increase the fmax, but decreases it instead?

Best regards,

Chris

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Ok ok then does that mean that the circuit with a pipeline depth of 1 stays idle until its result comes out?

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no. Lets imagine you have a pipeline delay of 10. You put one input in per clock tick. after 10 clocks you have just put ip10 into the system, and the first output arrives. In the pipeline are inputs 2-9, with results part completed.

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But are there conditions where increasing the pipeline depth doesn't increase the fmax, but decreases it instead?

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No. if you lengthen the pipeline, you decrease the amount of logic between registers.