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Ok ok then does that mean that the circuit with a pipeline depth of 1 stays idle until its result comes out?
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no. Lets imagine you have a pipeline delay of 10. You put one input in per clock tick. after 10 clocks you have just put ip10 into the system, and the first output arrives. In the pipeline are inputs 2-9, with results part completed.
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But are there conditions where increasing the pipeline depth doesn't increase the fmax, but decreases it instead?
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No. if you lengthen the pipeline, you decrease the amount of logic between registers.
Honored Contributor
