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OK, but as you said previously
FPGAs doesn't support both falling and rising edges of signal.
is that means every verilog module targeted for FPGA can't have sensitivity list without stating the edge of the signal?
Thanks
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Your code is not clocked, it is level sensitive, hence the latches.
If you wanted to be sentive to the edges, you would write:
always @(posedge clk or negedge clk)
begin
if (clk = '1') //rising edge action
else if (clk = '0') // falling edge action
end
This would create a double edge sensitive flop, which is not possible in FPGA. The following code is just level sensitive to the compiler, but not simulation as quartus will ignore the signals in the sensitivity list, and just use what is in the always block, so will not produce a flop:
always @(clk)
begin
if (clk = '1' ) // stuff to do while clock is '1'
else if (clk = '0') // stuff do while clock is '0'
end
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