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Lera_Dyakova's avatar
Lera_Dyakova
Icon for New Contributor rankNew Contributor
4 years ago

Latch-initialization in quartus prime

Hello,

Program was written using a latch. The latch has an initial initialization, for example = "0000001", but Quartus incorrectly initialized the latch, ="1111111" ,this was understood with the SignalTap. Why is that?

4 Replies

  • Alberto_R_Intel's avatar
    Alberto_R_Intel
    Icon for Occasional Contributor rankOccasional Contributor
    4 years ago

    Lera_Dyakova, Thank you for posting in the Intel® Communities Support.


    In order for us to provide the most accurate assistance on this matter, I just moved your thread to the proper department, they will further assist you with this topic as soon as possible.


    Regards,

    Albert R.


    Intel Customer Support Technician



  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    4 years ago

    Can you show some code?

    Also, it's recommended to use actual registers instead of building latches out of logic gates.

    • Lera_Dyakova's avatar
      Lera_Dyakova
      Icon for New Contributor rankNew Contributor
      4 years ago
      This is interesting , because the simulation shows the correct result. This is the code:
      library ieee;
      use ieee.std_logic_1164.all;
      use IEEE.std_logic_unsigned.all;
      entity running_LEDs is
      port (
      clk : in std_logic;
      led : out std_logic_vector(7 downto 0)
      );
      end running_LEDs;
      architecture rtl of running_LEDs is
      signal count : std_logic_vector(25 downto 0) := (others => '0');
      signal temp : std_logic_vector(7 downto 0) := (0 => '1', others => '0');
      signal rst : std_logic := '0';
      begin
      process (clk)
      begin
      if (rst = '1') then
      count <= (others => '0');
      elsif (rising_edge(clk)) then
      count <= count + 1;
      end if;
      end process;
      process (count)
      begin
      if count = 50000000 then
      rst <= '1';
      temp(7 downto 0) <= temp (6 downto 0) & temp(7);
      else
      rst <= '0';
      end if;
      end process;
      led <= temp;
      end rtl;