This is interesting , because the simulation shows the correct result. This is the code:
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity running_LEDs is
port (
clk : in std_logic;
led : out std_logic_vector(7 downto 0)
);
end running_LEDs;
architecture rtl of running_LEDs is
signal count : std_logic_vector(25 downto 0) := (others => '0');
signal temp : std_logic_vector(7 downto 0) := (0 => '1', others => '0');
signal rst : std_logic := '0';
begin
process (clk)
begin
if (rst = '1') then
count <= (others => '0');
elsif (rising_edge(clk)) then
count <= count + 1;
end if;
end process;
process (count)
begin
if count = 50000000 then
rst <= '1';
temp(7 downto 0) <= temp (6 downto 0) & temp(7);
else
rst <= '0';
end if;
end process;
led <= temp;
end rtl;
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