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Altera_Forum's avatar
Altera_Forum
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12 years ago

Just wiring two pins together

I'm sure this is a really easy answer, but I haven't been able to find it. Some signals were sent through my CPLD, someone thinking I might want to mess with them, and I don't for now, I just want to pass the signals (an I2C bus) through the device, basically wires between two pins.

Most of the signals are one way, so they are easy, the issue I'm having is with bidir signals. (I2C): Both the data and clock lines need to be bidirectional, and either the master or slave may be able to win control of the bus. I'm not sure how to do this, if I make them BUFFER's or INOUT's, they would be bidir, but I don't want to figure out who has control of the 'bus', since it is dealt with in hardware outside of my device. So if the Master is 1 and the Slave is 0, I don't want to force the bus to 1, since maybe it's suppose to be 0 (Like with clock stretching, which is slave initiated) In any case this seems like it's using a ton of LE's for something that is just a wire.

So...how do I make a dumb wire, with no logic between pins, can can I do this in an entity, which would make my code more readable, or is it a tool thing I have to do or in the top level?

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    You cannot do what you want. You have to put intelligence inside the chip.

    Think of what you are trying to do in terms of buffers. A '245 is the classic bidirectional buffer. The buffer output-enable and direction control needs to be controlled to drive the bus correctly.

    What if you want to connect to this bus, and you don't want direction control? You use a BusSwitch.

    The internal architecture of a buffer and a bus switch is different.

    If you look on the Linear Technology web site, you'll see lots of I2C repeaters and re-drivers. These parts are essentially intelligent devices that look at the logic levels. To create an FPGA I2C bridge, you'll basically have to do the same thing. If a signal is low on one side, then drive low on the other ... but remember which side the low first started from ... it seems like an 'easy' problem, but it gets tricky :)

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Thanks Dave-

    Does it make a difference if I don't want to connect to the 'bus' (Which is just point to point with one master and one slave) I have no interest in reading the signals, but a board has already been laid out, with the signals being routed through my device. If I could hold both pins in a high Z state, and jumper the pins together with a wire, or PCB trace, that would work fine, what I am trying to do is really just a wire between two pins.

    Best Regards
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    --- Quote Start ---

    If I could hold both pins in a high Z state, and jumper the pins together with a wire, or PCB trace, that would work fine, what I am trying to do is really just a wire between two pins.

    --- Quote End ---

    Yep, that would be what I'd do. If you can't get to the FPGA pins (if its a BGA), just wire the two nearest I2C devices on the two separate segments together. If the buses are routed as independent buses, then there should be independent pull-ups. If they're not too far apart, you could pull one set of pull-ups and jumper between the buses there.

    The other alternative is to treat the two buses as independent and put an I2C master/slave in the FPGA. If you have master on the two buses, you can program them to think of the FPGA logic as an I2C bridge.

    For now, a couple of wires would be the easiest solution.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    An additional comment regarding I2C repeaters.

    --- Quote Start ---

    If you look on the Linear Technology web site, you'll see lots of I2C repeaters and re-drivers. These parts are essentially intelligent devices that look at the logic levels. To create an FPGA I2C bridge, you'll basically have to do the same thing.

    --- Quote End ---

    There are more decicated repeaters available from NXP. They all depend on special interface hardware, in so far they can't be implemented in a FPGA without similar hardware that either senses different logic levels and/or pin currents.

    As Dave explained, the only way would be to implement an I2C bridge that decodes the bus protocol. It's behaviour would be partly different from a "wire".
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Thanks all, looks like I've got some work ahead of me then, at least I don't feel dumb about not being able to figure it out.