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Altera_Forum
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16 years ago

JK Flip-Flop - Quartus

Hi Guys,

Thx for are reading my Post,

So,

I'm a studant of Digital Eletronic and i need to make a "Flip-Flop JK" in Quartus II.

I maked the circuit, link: img338.imageshack.us/img338/2268/jkflipflop. png ( look the space, delete it)

And the waveform is: img169.imageshack.us/img169/2936/waveformjk. png ( look the space, delete it)

So, i think that this Waveform is Wrong, then i wanted a help to do it right.

What Value need I put in Ck (clock), J and K ?

I did the simulation using "Timing Mode".

Thx,

Leafar28

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    The circuit is no correct JK Flip-Flop. Basically, a Flip-Flop is expected as edge triggered circuit, the output must not change it's state on an input change other than an active clock edge (without considering additional asynchronous control inputs). The present circuit however changes it's output state outside active clock edges.

    I found the same circuit at wikipedia.de http://de.wikipedia.org/wiki/flipflop#jk-flipflop and an even completely erratic (functionless) "JK FlipFlop" at wikedia.org http://en.wikipedia.org/wiki/flip-flop_(electronics)#jk_flip-flop.

    For the systematic analysis of FF circuits, I appreciate the profound chapter latches and flip-flops in Enoch O. Hwang, digital logic and microprocessor design with vhdl. He shows, that besides a conventional master-slave structure also cascaded RS latches can constitute edge-sensitive behaviour. But three RS latches have to be combined for it.

    P.S.: I found an explanation in German literature, that claimed the unwanted output changes during CK = 1 as normal behaviour of a "JK FlipFlop", admitting, that the circuit isn't purely edge-triggered. But JK master-slave FFs don't show this problem. So I don't think that this is a convincing interpretation.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    As another supplement, I noticed that for 7473 "pulse-triggered" flip-flops, the J & K inputs must be stable during clock pulse, while newer 74LS73A are true edge triggered flip-flops.

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Your circuit, which is identical to the wikipedia.de circuit is basically working, but J and K inputs must be stable during CP = 1. Other JK circuits don't have this issue.

    As an additional problem, your waveforms are too fast (fCK = 500 MHz) to get reasonable results.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Ok, i understood.

    Now i need to do the Waveform, what values you advise me?
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    You should use a CP frequency that causes no timing violations and allows to recognize the interdependence of signal edges respectively levels from the waveform. I would prefer 10 or 20 MHz. If you want to operate the circuit according to it's specification, the J and K inputs should only change it's state while CP = 0 and keep a setup and hold time of a few ns, in other words, there edges should not coincide with CP as in your example.