JK Flip-Flop - Quartus

The circuit is no correct JK Flip-Flop. Basically, a Flip-Flop is expected as edge triggered circuit, the output must not change it's state on an input change other than an active clock edge (without considering additional asynchronous control inputs). The present circuit however changes it's output state outside active clock edges.

I found the same circuit at wikipedia.de http://de.wikipedia.org/wiki/flipflop#jk-flipflop and an even completely erratic (functionless) "JK FlipFlop" at wikedia.org http://en.wikipedia.org/wiki/flip-flop_(electronics)#jk_flip-flop.

For the systematic analysis of FF circuits, I appreciate the profound chapter latches and flip-flops in Enoch O. Hwang, digital logic and microprocessor design with vhdl. He shows, that besides a conventional master-slave structure also cascaded RS latches can constitute edge-sensitive behaviour. But three RS latches have to be combined for it.

P.S.: I found an explanation in German literature, that claimed the unwanted output changes during CK = 1 as normal behaviour of a "JK FlipFlop", admitting, that the circuit isn't purely edge-triggered. But JK master-slave FFs don't show this problem. So I don't think that this is a convincing interpretation.