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NEwton826's avatar
NEwton826
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5 years ago

Iteration limit reached

I have wrote a code for UART using FSM.I am getting the above error when I am using VWF .I known the part of the code that is causing the problem. TX_DATA_BITS. But can't understand why.

Please help me regarding it .

Thank you

3 Replies

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    5 years ago

    Can you show the full error message and a screenshot of your waveform? My guess is that add_count is going to 8 in the combinatorial logic before it is reset, which would exceed the number of bits in S.

    • NEwton826's avatar
      NEwton826
      Icon for New Contributor rankNew Contributor
      5 years ago

      @sstrell

      Here is the error pic.

      I don't think going to 8 is possible in my code because at 7 I reset it .

      • RichardT_altera's avatar
        RichardT_altera
        Icon for Super Contributor rankSuper Contributor
        5 years ago

        Have you try to simulate it using the Modelsim Intel FPGA Edition and check if the issue persist?