It adds 3 and subtracts 1 instead of adding just 1

If you dig through the Quartus synthesis documents then you will find that, as previously mentioned by some of the eminent VHDL chaps in this thread, the default value in the signal declaration is used by Quartus as a reset value.

But I have learnt from various VHDL courses that I have been on, that some synthesis tools ignore the default signal value and therefore for these tools you have to use a reset signal.

Whether you stick with default signal values or incorporate a reset signal (which you could generate internally), is up to you but just bear in mind that default signal values may not result in portable code.