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And try also to be sure that, form a hardware point of view, the logic is reset during the board power-up (using a simple RC circuit or some safer reset ICs which you can find in the market).
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A reliable power-up reset can also be achieved by using the FPGA internal reset, possibly supplemented by a delay. As long as no other reset sources are intended in the design, the external reset isn't actually necessary. Of course it does no harm to provide it anyway and keep it for possible design extensions.
The signal
nombre is initialized to the same state in FPGA internal power-up reset as by the external reset input. This also happens implicitely, if the initialisation expression is removed from the signal declaration.
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