It adds 3 and subtracts 1 instead of adding just 1

Hi rmc

Some thoughts for you:

1) I wouldn't use the variable that mmTsuchi suggested. Variables can be really useful but as various people have suggested they can catch you out if you're not careful. It will make no difference to your simulation or synthesis here - the synthesis process will strip it out anyway, so why bother!

2) Looking at your original code:

pr1: process(clk,reset,nombre)
    begin
    if reset='1' then
        nombre<="0101010101";
    else
        if(rising_edge(clk)) then
            nombre<=nombre+1;
        else
            nombre<=nombre;
        end if;
    end if;
    end process pr1;

I would remove the last else - this is why you're getting the messages about the sensitivity list. Altera have some guidelines on coding for synthesis (which are pretty much the same as other FPGA manufacturers) - check out page 6-42:

http://www.altera.com/literature/hb/qts/qts_qii51007.pdf?gsa_pos=1&wt.oss_r=1&wt.oss=coding%20style

If I were you I would strip out the last else - it's not doing anything anyway:

pr1: process(clk,reset)
     begin
    if reset='1' then
        nombre<="0101010101";
    elsif(rising_edge(clk)) then
            nombre<=nombre+1;
    end if;
     end process pr1;

This is then exactly in line with Altera's coding guidance (and the other silicon manufacturers); there is no gratuitous code; it is simple and clear.

Hope this helps

Cheers

batfink