Honored Contributor
Honored ContributorI found "Not-gate push back" on the Quartus Handbook Volum I section II 6.40, if someone want to take a look. Basically is what you have said on the forum.
Reading your posts I get some more questions :-)) 1. The using of variables, I understand the definition made before: use them when you need the result within the same clock time. Ok, this is a good rule of thumb, but: when I try to read signals that are not on the sensitivity list, compilator gives me a warning. I tried what mmTsuchi proposed: the use of a variable: Comptador: process (clk,reset) is variable c : std_logic_vector(9 downto 0); begin if reset='1' then count<="0000000000"; else if(rising_edge(clk)) then c:=count; count<=c+1; else count<=count; end if; end if; end process Comptador; Inside the if (clock_rising_edge) there is no more warnings. Now the warning is only for the else statement: count<=count. In this case the warning persists even when I use the variable here. My question: If there is a warning, it means that something is not properly done, so how can I fix it? If I read several signals, and I have to create a variable for each one is not a mess? so I have to ignore the warnings? 2. I don't know where I read it, but as I know it's good (it helps the compiler) to write the else statement always, even when it is an assigment count<=count. This stands always? also for the if (clock_rising_edge)? if there are no more signals on the sensitivity list the else statement should not happen, shouldn't, maybe if reset is made synchronous putting it inside the if (clock_rising_edge)? When someone starts on a new topic, as me with vhdl, all these tips are very useful, because one looses a lot of time in silly things. So I always thanks to who spent time on helping others. And really I'm learning a lot with these posts! thanks again :-)))
