Honored Contributor
Honored ContributorI totally disagree with Darkwave. For one thing, integer subtypes aren't in the same category as variables, and variables are totally fine in synthesizable VHDL. In fact, they are used all over the place to great success, e.g. for scratch pad calculations in a process and, of course, in a subprogram. You just need to understand the semantics of initialization and assignment. Some people don't realize that local process variables are static. Yes, no one should write VHDL code like it's a C program , but let's not toss the baby out with the bath water.
Not-gate push back is poor name for a simple and totally safe technique for FPGAs to implement preset when the device registers only power up to zero. The tool inverts the input and output of the register, which doesn't alter the synchronous functionality one bit but makes the register's fanout see a power-up state of VCC. Now, Quartus II doesn't alter the register name in order not to lose assignments (or need to migrate them to the new name). The inversion is essentially free in a LUT-based architecture (just push the inversion into the LUT masks of all the fanouts) in almost all cases, although you will see an occasional wire lcell implementing an inversion. The technique gets a bad rap because people see an inverted polarity when the observe the register in SignalTap II or Modelsim.
