Issues with Partial reconfiguration.

I tried to follow the document published in https://www.intel.com/content/www/us/en/programmable/documentation/ihj1482170009390.html I have a special doubt about this tutorial. When, exactly, should I export root_partition_static.qdb? Thanks a lot JohnT (Intel) Hi, May I know how do you implement your design using internal host? Is your data is being sent to the PR IP correct? You can refer to https://fpgawiki.intel.com/ AN 797: Partially Reconfiguring a Design on Intel Arria 10 ...<https://www.intel.com/content/www/us/en/programmable/documentation/ihj1482170009390.html> www.intel.com Partial reconfiguration (PR) feature allows you to reconfigure a portion of the FPGA dynamically, while the remaining FPGA design continues to function. You can create multiple personas for a particular region in your design, without impacting operation in areas outside this region. This methodology ... Deusdete Miranda Matos Junior Processamento de Alto Desempenho SENAI/CIMATEC Sistema FIEB | www.fieb.org.br<http://www.fieb.org.br> (71) 3462-8404 deusdete.junior@fieb.org.br