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Altera_Forum
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13 years ago

Issues with making a pipeline register in VHDL

I am currently having an issue with making a pipeline register in VHDL. A pipeline register is simply a register that connects two portions of a CPU pipeline together. It is easier to explain in code then on text in terms of its functions, so here is the code.


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity IF_to_ID_registers is
port (
      
	   fetched_instruction : in std_logic_vector(31 downto 0);
		
		clear: in std_logic;
		writeregister : in std_logic;
		send_zeros_instead : in std_logic;
		
		clk : in std_logic;
		
		output_instruction : out std_logic_vector(31 downto 0)
		
     );
end IF_to_ID_registers;
architecture Behavioral of IF_to_ID_registers is
signal instruction_register : std_logic_vector(31 downto 0); -- The internal register
begin
process(fetched_instruction, writeregister, clk, send_zeros_instead)
begin
if ( clk = '0' AND writeregister = '1') then 
instruction_register <=  fetched_instruction; -- Write the value into the register
end if;
if (rising_edge(clk)) then
if (send_zeros_instead = '1') then
output_instruction <= (others => '0');  -- Output zeros instead
else
output_instruction <= instruction_register; -- Output the register 
end if;
end if;
if (clear = '1') then  
instruction_register <= (others => '0');  -- Clear the register
end if;
end process;
end Behavioral;

The issue I have with this code is that during compilation I get the following error messages.


Warning (10492): VHDL Process Statement warning at PipelineRegisters.vhd(42): signal "clear" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10631): VHDL Process Statement warning at PipelineRegisters.vhd(25): inferring latch(es) for signal or variable "instruction_register", which holds its previous value in one or more paths through the process
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled
Warning (14025): LATCH primitive "IF_to_ID_registers:inst10|instruction_register" is permanently disabled

I am wondering what I did wrong. It seems like the issue stems from the instruction_register signal, but I cant tell what the issue is.

43 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    The issue is that I cant make it read the edge after, because then it won't make it to the next pipeline register. It seems like that I have to make the read level-based

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    It seems like I need to implement the register as an edge based write and a level based read. Is there any way how to do that?

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    the output of a register is avaible to whoever wants to read it at any time. No levels required. but be aware of the implications of asynchronous reads of registers (ie. metastability - reading during a change of value).