Issues while compiling Quartus-pro-18.0.0.219 cyclone10gx components with Cadence NCSIM ?

@modur​

Hi,

I have taken a look at your log file and the steps you described above.

To me it seems like problem is with your STEP4 you are using the file list from synthesis folder.

Solution 1:

Use the IP autogenerated script to bring up the simulation.

1. Go to directory <ip name>/sim/cadence
2. Execute ncsim_setup.sh

https://www.intel.com/content/www/us/en/programmable/documentation/zcn1513987282935.html#mwh1409958648983

Solution 2:

1. During the IP files generation make sure you generate simulation file, From IP Parameter Editor Window click Generate HDL > In the simulation tab change Create simulation Model from none to Verilog
2. Use the IP file list documented under directroy <ip name>/sim/common/ncsim_files.tcl "proc get_design_files "

Let me know if this is helpful.

Thanks,

Arslan