New Contributor
New ContributorHi Arslan,
I think you've got the problem.Below are the steps which i've performed in Quartus with NCSIM;
Step1: I opened Quartus Prime Pro 18.0 edition in GUI mode and ran EDA Simulation Library Compiler .
Please follow the attachment N0:1 for the list of options chosen by me.
Step2: Once i compiled the Library with target simulator NCSIM version 15.20, we can see cds.lib and
hdl.var and other log files in the target output directory.
Step3: From the above version of Quartus, I've downloaded the LVDS SERDES IP for compiling with
NCSIM.
Step4: I've flist_dut to compile the lvds files;
../../../../rtl/lvds_receiver_x8/altera_lvds_core20_180/synth/altera_lvds_core20.sv
../../../../rtl/lvds_receiver_x8/altera_lvds_core20_180/synth/altera_lvds_core20_pll.v ../../../../rtl/lvds_receiver_x8/altera_lvds_core20_180/synth/lvds_receiver_altera_lvds_core20_180_ze3vd7i.sv
../../../../rtl/lvds_receiver_x8/altera_lvds_180/synth/lvds_receiver_altera_lvds_180_6yosg6y.v
../../../../rtl/lvds_receiver_x8/synth/lvds_receiver.v
Step5: i've Makefile for NCSIM with below switches ;
irun -access rw $(INCLUDE) $(DEFINES) -ALLOWREDEFINITION -timescale 1ps/1ps -SVSEED ${SEED} -uvmhome $(UVM_HOME) -WORK work -CDSLIB ${CDS_LIB}/cds.lib -hdlvar /home/moduru/Documents/projects/Quartus_ncsim_lib/hdl.var -sv ....
Step6: After compiling; the NCSIM giving elaboration errors as below;
irun.log has shared....please follow the attachment.
