Issues while compiling Quartus-pro-18.0.0.219 cyclone10gx components with Cadence NCSIM ?

Hi,

I tried to compile with cds_lib files and the elaboration went smooth.

Thanks Musman for suggesting the tcl file creation.

regards,

Mahesh.

Hi Mahesh,

It seems like you are trying to simulate an Intel FPGA IP in NCSIM and facing some Error.

Can you confirm if you are using the AUTO GENERATED script to bring up the simulation ?

Which IP are you using, I can try to replicate and look into it ?

What version of NCSIM was used ?

Thanks,

Arslan

Hi Arslan,

I think you've got the problem.Below are the steps which i've performed in Quartus with NCSIM;

Step1: I opened Quartus Prime Pro 18.0 edition in GUI mode and ran EDA Simulation Library Compiler .

Please follow the attachment N0:1 for the list of options chosen by me.

Step2: Once i compiled the Library with target simulator NCSIM version 15.20, we can see cds.lib and

hdl.var and other log files in the target output directory.

Step3: From the above version of Quartus, I've downloaded the LVDS SERDES IP for compiling with

NCSIM.

Step4: I've flist_dut to compile the lvds files;

../../../../rtl/lvds_receiver_x8/altera_lvds_core20_180/synth/altera_lvds_core20.sv

../../../../rtl/lvds_receiver_x8/altera_lvds_core20_180/synth/altera_lvds_core20_pll.v ../../../../rtl/lvds_receiver_x8/altera_lvds_core20_180/synth/lvds_receiver_altera_lvds_core20_180_ze3vd7i.sv

../../../../rtl/lvds_receiver_x8/altera_lvds_180/synth/lvds_receiver_altera_lvds_180_6yosg6y.v

../../../../rtl/lvds_receiver_x8/synth/lvds_receiver.v

Step5: i've Makefile for NCSIM with below switches ;

irun -access rw $(INCLUDE) $(DEFINES) -ALLOWREDEFINITION -timescale 1ps/1ps -SVSEED ${SEED} -uvmhome $(UVM_HOME) -WORK work -CDSLIB ${CDS_LIB}/cds.lib -hdlvar /home/moduru/Documents/projects/Quartus_ncsim_lib/hdl.var -sv ....

Step6: After compiling; the NCSIM giving elaboration errors as below;

irun.log has shared....please follow the attachment.

the irun.log has the error information.

Please help in this regard?

Thanks,

MAHESH.

@modur​

Hi,

I have taken a look at your log file and the steps you described above.

To me it seems like problem is with your STEP4 you are using the file list from synthesis folder.

Solution 1:

Use the IP autogenerated script to bring up the simulation.

1. Go to directory <ip name>/sim/cadence
2. Execute ncsim_setup.sh

https://www.intel.com/content/www/us/en/programmable/documentation/zcn1513987282935.html#mwh1409958648983

Solution 2:

1. During the IP files generation make sure you generate simulation file, From IP Parameter Editor Window click Generate HDL > In the simulation tab change Create simulation Model from none to Verilog
2. Use the IP file list documented under directroy <ip name>/sim/common/ncsim_files.tcl "proc get_design_files "

Let me know if this is helpful.

Thanks,

Arslan

Hi,

I've successfully created the ncsim_files.tcl. But, couldn't run this tcl...

Can you please suggest me the command line option to run the ncsim_files.tcl?.

Thanks,

regards,

Mahesh