Issue with Quartus Prime PRO for Stratix 10 when using a string type in a VHDL project.
Hello, When using "Quartus Prime Pro 20.1" software with "Stratix 10" chip, I have a problem with VHDL string type in my projects. At the same time, I don't have this problem when using "Quartus Pri...
Dear KhaiY,
Thank you for your message and for remembering my problem.. but I'm not
ready yet. :-( I am very sorry about this delay. I have so many
different problems lately.
I tried to prepare a code showing the issue but I didn't have enough
time. We have the end of the semester here at the university and I have
hundreds of students to whom I have to give grades. And because of
coronavirus it is a crazy time. I'll prepare the code as soon as
possible.
As to the issue:
Solving this Stratix_10 problem in Quartus Prime Pro is very important
to me.
In general, I think the problem appears when sharing string data between
different entities.
I need to prepare a short code showing this problem, but as I told you
before, each compilation of the simplest code for Stratix_10 that I try
to test takes me at least 9 minutes! which means: only seven tries take
about an hour. This is not the case with another family of FPGAs (MAX10,
Cyclon_IV and others).
I promise that I'll do my best to prepare the code showing the issue as
soon as possible. It is important for me because without your help in
solving this problem, I can't and I won't be able to use my own IPs
codes for the Stratix_10 chips. :-(
Best Regards,
(jd)
Hi,
Motivated by your message here and your willingness to help, I spent the
last night preparing a code showing the problem. I enclose it at the end
of this message. The code doesn't make any sense, but it's rather
compliant with the VHDL standard and compiles correctly for MAX10 and
Cyclone_IV FPGA chips. But when I choose Stratix 10 (and also Cyclone
10, which I discovered yesterday) Quartus Prime shows errors.
if there is:
set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE ON
I get exception error:
"Sorry! The Quartus Prime software quit unexpectedly."
if there is:
set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE OFF
I get processing errors:
Error(13076): The node "instance_1|str_1[1][0]" has multiple drivers.
Error(20073): "constant GND" is one of the multiple drivers.
Error(20073): "non-tri-state driver "str_1[1][0]"" is one of the
multiple drivers.
Error(13076): The node "instance_1|str_1[1][1]" has multiple drivers.
Error(20073): "constant GND" is one of the multiple drivers.
Error(20073): "non-tri-state driver "str_1[1][1]"" is one of the
multiple drivers.
Error(13076): The node "instance_1|str_1[1][2]" has multiple drivers.
Error(20073): "constant GND" is one of the multiple drivers.
Error(20073): "non-tri-state driver "str_1[1][2]"" is one of the
multiple drivers.
Error(13076): The node "instance_1|str_1[1][3]" has multiple drivers.
Error(20073): "constant GND" is one of the multiple drivers.
Error(20073): "non-tri-state driver "str_1[1][3]"" is one of the
multiple drivers.
Error: Failed to synthesize partition
As you can see, the errors say that "str_1" has multiple drivers but
there is only one explicit place where "str_1" is driven. The command:
str_1:="ABCD";.
These errors disappear when you do a tiny change in the code. For
example, they dissappear when you comment the line "data<=vec_1(3 downto
0);". It makes no sense to me because this line does nothing with
"str_1"! The errors also disappear when you change:
if s2/=s1 then s2:=s1; str_1:="ABCD"; end if;
to only:
str_1:="ABCD";
which is completely strange to me, but I understand that the driver here
becomes stronger then.
Of course, the errors also disappear after changing the direction
"inout" to "in" for "str_1" in entity "e2", but in my operative code I
need bidirectional "str_1", and with this "inout" everything works fine
for MAX10 and Cyclone_IV.
And why did Quartus Prime put the GND driver in the "e2" entity, if it
leads to an obvious drivers conflict?
I hope that below code will help you find the cause and then create a
fix. Here is the code with two entities:
###########################################################
Something has cut the code, so here it is again:
###########################################################
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
entity e1 is
port(
data : out std_logic_vector(3 downto 0);
clk : in std_logic
);
end e1;
architecture arch1 of e1 is
component e2 is
port(
data : out std_logic_vector(3 downto 0);
clk : in std_logic;
str_1 : inout string(1 to 4);
vec_1 : inout std_logic_vector(31 downto 0)
);
end component;
shared variable str_1 : string(1 to 4);
shared variable vec_1 : std_logic_vector(31 downto 0);
shared variable s1, s2 : std_logic;
begin
instance_1 : e2 PORT MAP (
data => data,
clk => clk,
str_1 => str_1,
vec_1 => vec_1
);
process
begin
wait until clk'EVENT and clk='1';
s1 := not s2;
end process;
process
begin
wait until clk'EVENT and clk='1';
if s2/=s1 then s2:=s1; str_1:="ABCD"; end if;
vec_1(7 downto 0):= conv_std_logic_vector(character'pos(str_1(1)),8);
end process;
end arch1;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity e2 is
port(
data : out std_logic_vector(3 downto 0);
clk : in std_logic;
str_1: inout string(1 to 4);
vec_1: inout std_logic_vector(31 downto 0)
);
end e2 ;
architecture arch1 of e2 is
begin
process
variable clk2: std_logic;
begin
wait until clk'EVENT and clk='1';
data<=vec_1(3 downto 0);
clk2:= not clk2;
end process;
end arch1;
###########################################################
Best Regards,
(jd)
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