Forum Discussion
KhaiChein_Y_Intel
Regular Contributor
5 years agoHi JD,
I conveyed your concern to the team, please see the reply below:
If customer do not want to change their design, the only option for them before we fix the issue, is to turn off state machine inference using the following qsf for the whole design. It may not be desirable though but it will unblock customer from this error.
set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE OFF
Could you add the above setting in the QSF file?
Thanks.
Best regards,
KhaiY
- JDlug5 years ago
New Contributor
Hi, Thank you very much for your answer. It's not that I don't want to change the design. Modifying everything that already works great with other chips will take a long time and is illogical. I did many tests with the "ENABLE_STATE_MACHINE_INFERENCE OFF" assignment you wrote about. It helped with this very simple code that I put here, and the window of the unexpected error message does not appear now, but it did not help in my real projects. :-( I still have another problems. For example, in a certain project without the setting: "set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE OFF" I get: Error(13787): VHDL error at fpga_net.vhd(378): "statement" is not synthesizable since "eth.str_1[7].'�'" does not hold its value under NOT(clock-edge) condition However, when in the same project I put this setting: "set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE OFF" to the .QSF file, the above error disappears but many other errors such as this appear: Error(13076): The node "eth_instance_1|data.str_1[1][4]" has multiple drivers. Error(20073): "non-tri-state driver "eth.str_1[1][4]"" is one of the multiple drivers. Error(20073): "constant GND" is one of the multiple drivers. This is strange, because in my design there is only one place where I set the str_1 variable. I don't really see any reason for these errors in my code. And again, all the above mentioned errors do not show up when building exactly the same project but for MAX10, Cyclone II, Cyclone III or Cyclone IV FPGAs. All my projects with these chips (after a very quick compilation) work perfect and without problems. Problems happen only with Stratix 10. The Quartus Prime shows confusing errors only when I use STRING type, and there are no errors at all when I do not use STRING type. But then, the compilation inexplicably takes a long time. The "ENABLE_STATE_MACHINE_INFERENCE OFF" does not solve the issue. :-( The good news is that you've wrote that there will be a fix for this. Thank you. I understand that this may take some time and I will be patient. If there is anything more I could tell you about my problems with Quartus Prime to help find the bug - let me know. I'll do my best to help. Thank you. (jd)