Hi,
--- Quote Start ---
The numerator of the divider is 2 32 bit words (as I could not use a 64 bit constant) which has a value of
x5a00000000000000, the denominator is a 40 bit value, 250,000,000 (
xee6b280) in my example. If I do this division in decimal, the answear comes out fine, but using the calculator in windows and doing the division in hexadecimal, the answear comes out
incorrect (
x60a302f9d)
--- Quote End ---
i think x60a302f9d is a correct result (not very very very carfully verified). I see You work in unsigned :
signed give same result I think (in respect of size) but not fixed float, neither float IEEE...
What "result" do you expect ? Are you tired ;-) ? Am I wrong ?
Another thing I notice :
Your design employes very "hungry" operations in term of logical ressources.
No registers between operations, no pipeline make your design work in (very) low frequency.
Do you aim to implement it in a FPGA (or CPLD) ?